1. Field of the Invention
This invention relates to the manufacture of thin film transistors (TFTs) by the deposition of polysilicon.
2. Description of the Related Art
FIG. 1 of the accompanying drawings illustrates the first steps in a well-known process for the formation of a polysilicon TFT. Firstly, a layer (FIG. 1(a)) of silicon dioxide is deposited on a glass substrate 2. A layer 3 of polysilicon is then formed over a region of the silicon dioxide layer. A further area 4 (FIG. 1(b)) of silicon dioxide is formed on the layer 3, and a gate region 5 of polysilicon is formed in alignment with the area 4. The gate region 5 and regions 6 and 7 of the layer 3 projecting beyond the gate region are then doped (FIG. 1(c)) by ion implantation to form gate, source and drain regions respectively, of n.sup.+ polysilicon. Contact layers (not shown) are subsequently formed over the regions. During the ion implantation process, the gate region 5 acts as a mask, which should prevent doping of the central region 8 of the layer 3. However, unless very careful control over the ion implantation process is maintained, the doped regions 6 and 7 will extend underneath the gate region 5, forming parasitic capacitances between the gate and the source and between the gate and the drain. The capacitances will reduce the speed of operation of the device.
Furthermore, the ion implantation process accounts for a major part of the cost of forming the device. Moreover, ion implantation is not suitable for the production of TFTs over a large area.
In an alternative known process, (not shown), the lower silicon dioxide layer is covered with a mask having apertures through which doped source and drain regions similar to the regions 6 and 7 are deposited. A layer of polysilicon is formed over those regions, followed by a silicon dioxide layer. A gate region similar to the region 5 is then formed centrally on the silicon dioxide layer. There is a considerable likelihood that the gate region will overlap the edges of the source and drain regions, and parasitic capacitances such as mentioned above will result.